ISRO CSE 2016
Q48.
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor isQ49.
What is the sum to infinity of the series,3+6 x^{2}+9 x^{4}+12 x^{6}+\ldots \text { given }|x| \lt 1Q50.
At a particular time of computation the value of a counting semaphore is 7. Then 20 P operations and x V operations were completed on this semaphore. If the new value of semaphore is 5, x will be